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oa Reduced switch count asymmetrical flying capacitor multi-level inverter for variable speed drives application
- Publisher: Hamad bin Khalifa University Press (HBKU Press)
- Source: Qatar Foundation Annual Research Forum Proceedings, Qatar Foundation Annual Research Forum Volume 2013 Issue 1, Nov 2013, Volume 2013, EEP-044
Abstract
This paper discusses a reduced switch count topology of multi-level three-phase voltage source inverter for variable speed drive applications. In the investigated topology, the number of power switching devices and the number of capacitor/neutral voltage clamping devices are drastically reduced when compared with the existing Neutral Point Clamped (NPC), Flying capacitor (FLC) and Cascaded H-bridge (CHB) multilevel solutions. The number of devices for different types of inverters are shown in Table 1. The number of devices is reduced more when number of output level is increased. The converter configuration is proposed in the literature for seven-level and thirty-one level single-phase output and named as asymmetrical flying capacitor or Packed U cell (PUC) inverter. The same concept is extended in this paper for three-phase output and for variable speed drives application. The emphasis is placed in the development of three-phase seven-level voltage source inverter with asymmetrical flying capacitor configuration. The number of power semiconductor switching devices used in the proposed topology is only 50% of the number used in conventional NPC/FLC/CHB. Hence there is a saving of 50% in number of devices. The proposed solution offers transformer-less topology with reduced dv/dt and reduced switching losses. Modeling, simulation, control and implementation is conducted and reported in this paper. The developed model is validated using Matlab/Simulink simulation and experimentally verified. Simple multiple carrier-based Pulse Width Modulation techniques (PWM) is employed. Unlike the NPC inverter, this topology does not require any clamping diodes and is also free from issues like neutral point fluctuations. A carrier based PWM technique combined with a PI controller for balancing of the capacitor's voltages is used for the control of the seven-level inverter. Here balancing is in the sense that the voltage across the clamping capacitor is to be maintained at 1/3rd of dc link voltage. The major disadvantage of the proposed topology is the requirement of isolated dc supplies. The problem may also arise in case of dc link voltage unbalance. The electric drive system employing the proposed inverter topology find application in high power ac drives such as in oil & gas industries, electric/hybrid electric vehicles, ship propulsion, traction etc.The proposed topology is shown in Fig. 1 and sample simulation result is presented in Fig. 2. The detailed results and theoretical analysis will be reported in the full paper. The results will also include the effect of unbalanced dc link voltage.